Integrated circuits are typically packaged in a single chip or `monolithic` configuration which, in turn, is soldered or plugged into a printed circuit board, or other type of interconnect support substrate. In a multi-chip `hybrid` package, several devices are assembled into a single package. Such a packaging scheme has the advantages of reduced weight, size and, occasionally, circuit performance. In an effort to further enhance packaging density, edge-wise or vertically stacked multi-chip packaging assemblies have been proposed. In such configurations, rather than array a plurality of devices in what is essentially a single dimensional, or planar, layout, the devices are arranged on top of one another in a `stack` or `layered` assembly.